1. Field of the Invention
The present invention relates to the manufacture of semiconductor integrated circuits and, in particular, to a method of forming conductive vias between conductive layers in an integrated circuit structure for maximum size, optimum shape and lowest possible via resistance.
2. Discussion of the Related Art
Integrated circuits commonly use multi-level conductive interconnects to reduce the layout area required for the tens or hundreds of thousands of active semiconductor devices that typically form an integrated circuit. This reduction in layout area is possible because the two or more conductive layers used in multi-level interconnect schemes are separated by dielectric layers that allow crisscrossing of the separated conductive layers without electrical shorting. Intentional connections between conductive layers separated by a dielectric are created by forming small apertures in the dielectric and filling the aperture with a conducting material such as aluminum. These connections, which are usually made between consecutive conductive layers, are known as vias.
As semiconductor device geometries continue to shrink into the submicron range, it is increasingly difficult to maintain planar conductive and dielectric surfaces during the formation of multi-level interconnect structure. This lack of planarity can cause several problems. For instance, if the underlying topography coated by a photoresist layer contains abrupt steps due to lack of planarity, the photoresist layer""s thickness will not be uniform. This can occur, for example, when photoresist is applied to overlie features formed earlier in a semiconductor device process that protrude from the surface of a wafer. Photoresist cannot be applied uniformly over such a topography. This nonuniformity in thickness can lead to some regions of the patterned photoresist layer being inadequately thick to protect underlying features during a later etching step and other regions being excessively thick so that the full thickness of the photoresist layer cannot be exposed due to the depth-of-focus limitations of photolithography at sub-micron dimensions. Also, poor planarity of conductive and dielectric layers promotes poor step coverage which increases sheet-resistance, susceptibility to current-stress failure, electromigration problems and the probability of electrical opens. In addition, poor planarity in underlying conductive or dielectric layers formed earlier in a semiconductor device process further increases the difficulty of establishing planarity in overlying layers formed later in that process.
Another difficulty associated with via formation for multi-level interconnects in sub-micron semiconductor devices is the alignment of upper and lower conductive layers with the aperture formed in the intermediate dielectric layer for a via. This alignment is difficult because of the small distance between device features in sub-micron devices and the reduced tolerance available for alignment errors. Misalignment of a via relative to connected upper and lower conductive layers can lead to reduced device yield, increased via resistance and poor metal coverage in the via. For example, in a standard via, misalignment of the via relative to the lower conductive layer results in overetching into the dielectric underlying the lower layer, thereby increasing the aspect ratio of the via opening and preventing adequate step coverage when later filling the via with metal; the result is a poor contact interface in the via and increased via resistance. Misalignment of an upper conductive layer relative to a via results in overetching, or notching, of the lower layer; the notched lower layer exhibits increased current density and is, thus, more susceptible to failure from electromigration or current stress.
In many semiconductor devices, the layout dimensions of upper and lower conductive layers connecting to vias are extended in the vicinity of the via to form a layout frame, or head, around the via. This is known as framing the via. The frame provides additional alignment margin such that if partial misalignment of an upper and lower conductive layer relative to the intended via location occurs, the actual formed via will still overlie a portion of a lower layer or underlie a portion of an upper layer. However, an adverse effect of using framed vias in a semiconductor device layout is that the layout area is substantially increased.
A third difficulty associated with via formation for multi-level interconnects in sub-micron semiconductor devices is the contact resistance of the vias caused by polymer residue formation during the etching of the vias. These residues are typically formed during plasma etching and may contaminate the bottom of the via, thus causing a poor metallurgical contact between the lower layer and the conductive material of the via.
Accordingly, a need has existed for a method of forming a via for connecting multi-level interconnects in sub-micron semiconductor devices that improves the surface planarity of formed conductive and dielectric layers, reduces problems associated with via misalignment, reduces contact resistance problems associated with polymer residues and lowers associated manufacturing costs.
Commonly-assigned U.S. Pat. No. 5,904,569, which issued to Vassili Kitch (the inventor in this application) on May 18, 1999, discloses a process for forming a via in a semiconductor device that uses a self-aligned metal pillar, to connect conductive layers separated by a dielectric. In accordance with the teaching of the Kitch ""569 patent, a first conductive layer is formed on a semiconductor substrate, followed by formation of a second conductive layer on the first conductive layer and a third conductive layer on the second conductive layer. The three conductive layers are then patterned and etched to form a patterned stack of the first, second and third conductive layers. A dielectric material is then deposited to fill the gaps between the patterned stack of the first, second and third layers. The wafer is then planarized, typically using Chemical Mechanical Processes (CMP), to expose the patterned portion of the upper, third conductive layer of the stack. The third conductive layer is then etched, forming a pillar, using the second conductive layer as an etch stop; that is, the etch chemistry etches the third conductive layer, but does not substantially react with the second conductive layer. A second dielectric layer is then deposited to substantially fill the gaps created by the patterning and etching of the third conductive layer. CMP is again used to planarize the wafer and to expose the top of the pillar. A fourth patterned conductive layer is then formed on the wafer overlaying the exposed top of the pillar. The result is an interconnect structure that includes the first and second (etch stop) conductive layers as lower metal, the fourth conductive layer as upper metal and the third patterned conductive layer providing via pillars between lower and upper metal.
Referring to FIG. 1, as discussed above, accurate alignment of the via hole 10 between a lower metal layer 12 and an upper metal layer 14 can be difficult to achieve. To ensure proper alignment and still maintain acceptable packing density, the size of the etched via hole 10 is often made smaller than the dimensions of the two metal layers, as shown in FIG. 1, leading to the increased via resistance and associated problems discussed above.
FIG. 2 shows an example of upper metal 20 passing over a wider portion of lower metal 22, thus enabling the using of multiple via holes 24 at the intersection of the lower metal 22 and upper metal 24 to help alleviate the via resistance problem.
As evidenced by the above, it would be highly desirable to have available a technique that could provide the maximum allowable via size between upper and lower metal interconnect structures.
The present invention provides a technique for laying out vias between conductive layers in an integrated circuit structure utilizing existing conventional Metal n and Metal n+1 layout databases. This allows for interconnect vias to always be optimized in size and shape for existing Metal n and Metal n+1 interconnects, thus providing the lowest possible interlayer resistance, which in turn provides the best possible circuit performance and reliability.
That is, in accordance with the present invention, a first database (Metal n) is created that defines a lower conductive layer. A second database (Metal n+1) is created that defines an upper conductive layer. Selected intersections of the first and second databases are then defined to create a third database (via n) that defines a via pattern between the lower conductive layer and the upper conductive layer.
Further objects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings.